FIG. 1 shows a RAM used as a ROM and configured as a finite state machine. Some of the finite state machine (FSM) input wires carry input signals and some carry feedback signals to tell what state the machine is in. Together, these signals form the address of a memory cell in the ROM. Data output from the addressed word of the ROM goes on data-out wires, some of which are state wires that feed back to the address input ports, and some of which form the FSM output. In a state machine some of the address bits are controlled by output data fed back from the block RAM and other address bits are provided externally.
FIG. 2 shows an example state machine that can be implemented by the ROM structure of FIG. 1. This state machine moves up one state or remains in the highest state in response to a data value of 01. It moves down one state or remains in the lowest state in response to a data value of 00. And it resets to state 00 in response to a data value of 10 or 11. In other words, the first bit serves as a reset signal. FIG. 3 shows the addresses and data values to be stored in the ROM structure of FIG. 1 for implementing this state machine. Sixteen memory locations are required in order to get the fast reset to state 00 required by the state machine of FIG. 2.
It would be preferable to use fewer memory locations to implement such a simple state machine.